In telecommunication systems, the receiver is assumed to be able to generate a set of local clock signals whose characteristics are identical to the characteristics of the signalling alphabet in use at the transmitter. The alignment of the locally generated clock signals with the clock information extracted from the received signal referred to as the reference clock is achieved with the use of a synchronization reference selected in relation with the modulation protocol employed and extracted from the incoming signal.
For low frequency applications such as frame and symbol synchronization, this alignment is usually accomplished with a DPLL (digital phase locked loop). The main components of the DPLL synchronizer include a DPD (digital phase detector) for measuring the phase error between the reference clock and a locally generated clock and a DCO (digitally controlled oscillator) for generating that local clock.
The timing constraints imposed over the years by state-of-the art technology applications caused the DPDs to rapidly evolve to provide enhanced phase error measurement accuracy and resolution for improving the performance of DPLL-based designs. However, the DPDs used in present day synchronizers are designed with digital counters based on flip-flop gate arrangements which are known to exhibit large propagation delays. As such, they do not present a satisfactory phase error resolution.
In order to meet the strict requirements of today's synchronization applications, the DPDs necessitate additional circuitry to eliminate counter-wraps and phase buildups for improving the performance of the synchronizers. However, this complicates the design and heavily affects synchronization costs.
Accordingly, there is a need for a DPD circuit for providing phase error measurements with high resolution and improved accuracy which is simple to implement and cost-efficient.